The basic architectural specifications of Lovelace Nvidia were revealed

According to the revelations that long ago revealed almost all the information about Nvidia’s Ampere graphic architecture, the Green team has been working on its next architecture for graphics cards for some time now. Ida Lovelace The mathematician will use it. Meanwhile, it seems that the completion of the development of Hopper architecture is currently delayed indefinitely, and Lovelace architecture is likely to replace Hopper. One of the hallmarks of lil architecture is a structure called MCM or Multi-Chip-Module. In this type of structure, several chips are placed in one processing package.

Nvidia always uses the names of prominent people for its graphic architectures. According to many historians, Ida Lovelace was the first serious fan of computers and the first person to understand the analytical engine (Analytical Engine) In addition to pure computing, it has other uses as well. Not to mention the design of the analytical engine for the first time Charles Babbage Offered. Lovelace also proposed the first algorithm based on a device such as the Charles Babbage Analytical Engine. All of this happened almost half a century ago Alan Turing Complete his work and design all-purpose computers in the midst of World War II.

Nvidia may have delayed Hopper’s architecture to work on Lovelace architecture

As mentioned, Nvidia is keen to use the names of leading scientists, mathematicians, and physicists for its graphic architectures, and the company’s new architecture, Lovelace, is no exception. Videocardz says it has obtained evidence in the Nvidia store that the rumors centered on the choice of Lovelace as the name of the next generation of Green Team graphic architecture.

If you look at the video Take a look at what Nvidia released at GTC 2018, not just the name Ida Lovelace, but other names that are likely to be chosen as the names of Nvidia’s next-generation architectures. That means probably Jin Sun Huang, The CEO of Nvidia, has announced the names of all of his company’s future architectures indirectly in the keynote address of the GTV 2018 conference.

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The names of the scientists include Ida Lovelace at Nvidia's GTC 2018 event

Several news outlets, citing sources who wished to remain anonymous, have claimed that Lovelace will be based on a five-nanometer lithography. Since Nvidia has taken over the task of producing its graphics chips from Samsung, we do not currently know the five-nanometer lithography of Lowell’s architecture belonging to TSMC or Samsung.

Don’t forget that according to a new report released some time ago in South Korea, Nvidia has placed an order for six-nanometer chips. This means that either before the launch of Lovelace Nvidia introduces another architecture with six-nanometer lithography or Lovelace is to be built on the basis of six-nanometer lithography. Kopite’s Twitter account has a long history of disclosing detailed information about Ampere architecture. He claims that Lovelace relies on fifty-nanometer lithography.

Kopite claims that Hopper architectures and graphics cards based on the MCM design style are currently delayed. This news will definitely not be happy for those who are interested in the world of technology; Because MCM-based GPUs offer more processing power than today’s GPUs and can break records. If we are still going to depend on integrated designs, the efficiency of the chips is still going to be a serious problem.

To better understand the situation, it is better to do calculations. Consider a chip with an area of ​​484 mm2 (chips such as the Vega 64). The dimensions of this chip are 22 by 22 mm. Dividing this integrated chip into four chips measuring 11 by 11 millimeters gives you the same level of access (484 millimeters) and ultimately increases efficiency.

You may ask yourself how? According to estimates, the 300mm wafer should be able to make 114 integrated chips (22 x 22) or 491 smaller chips (11 x 11). Since the second method requires four smaller chips to create integrated chips, we will eventually deal with 122 484 mm square MCM chips. This means a 7.6 percent increase in efficiency.

Comparison of integrated wafer with MCM wafer

When it comes to larger chips, the rate of return increases. The ultimate lithographic technique with a reasonable yield is approximately 815 mm2; So on 300mm chips we can fit approximately 64 of these chips (28.55 by 28.55) or 285 smaller chips (14.27 by 14.27). In such a chip, a total of 71 design-based chips MCM is associated with an increase in efficiency of approximately 11%.

The numbers we have mentioned are based on some estimates and are obtained using incomplete calculations; Because in our calculations, we have not included important factors such as the efficiency of packaging techniques and the characteristics of rectangular chips and other optimizations that are based on the shape of the wafer.

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However, the same numbers can give us an overview of the story. Also, our calculations do not include other factors such as increasing profits by reducing waste. A defective 815 mm2 chip has much more waste than a 203 mm2 chip.

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However, at present we do not know much about the architecture of Lovelace Nvidia, except for the codename and lithography; However, in the not too distant future, we will definitely hear more about it.

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